The integrated circuit (“IC”) industry faces the challenge of reducing yield loss caused by defects during manufacturing. These defects can be either random defects or systematic defects. Random defects, as the name implies, result from random occurrences such as particulate contamination. Systematic defects are non-random and result from problems with the manufacturing process and/or IC design. Systematic defects will reoccur when a manufacturer uses a similar process or IC design. A designer may be able to categorize or anticipate certain systematic defects based on a shape or feature pattern on an IC.
As the IC industry moves to smaller IC features, an increasing number of various subtle design processes exist for manufacturing the ICs. Each subtle design process may cause unique systematic defects, thus increasing the number and type of systematic defects present in a manufactured IC. Circuit designers use a combination of various tools to reduce these systematic defects. While these tools help designers to account for systematic defects during the IC design process, the tools are often poorly integrated, if integrated at all, thus making designing robust fault free ICs difficult. Designers need a fault diagnostic system which allows for conducting fault analysis and visualization of the simulated faults in a schematic or layout.